Webinar Date: Thursday, July 6, 2017
Time: 12:00 PM Noon (EDT)
Speakers: Erik Jan Marinissen, Principal Scientist, imec; Jörg Kiesewetter, Director of Engineering, Cascade Microtech GmbH; and Ken Smith, Principal Engineer, FormFactor
Location: on the Web
Event Details & Registration: spectrum.ieee.org/webinars
Summary: In the context of pre-, mid-, and post-bond testing of dies in a 2.5D- and 3D-stacked IC, a fully automatic test system for characterizing advanced probe cards able to probe on large-array fine-pitch micro-bumps (such as JEDEC’s Wide-I/O Mobile DRAM interfaces) has been specified, developed, installed, and brought into full operation. The system is based on a CM300 probe station from Cascade Microtech (now FormFactor) and National Instruments PXI test instrumentation and complemented by in-house-developed software for automatic test generation and data analysis and visualization. The system is successfully used in conjunction with FormFactor’s Pyramid Probe RBI probe technology on Wide-I/O 1 and 2 micro-bump arrays on ø300mm wafers designed and manufactured by imec. This presentation describes the various system components in hardware and software, and experimental results obtained with several test wafers.
Erik Jan Marinissen is Principal Scientist at imec, the Leuven, Belgium research institute, where he is responsible for research on test and design-for-test, covering topics as diverse as TSV-based 3D-stacked ICs, silicon photonics, CMOS technology nodes below 10nm, and STT-MRAMs. In addition, he is Visiting Researcher at Eindhoven University of Technology, the Netherlands. Previously, he worked at NXP Semiconductors and Philips Research Laboratories in Eindhoven. Marinissen holds an MSc degree in computing science and a PDEng degree in software technology, both from Eindhoven University of Technology. He is author or co-author of 280 journal and conference papers and a named inventor on fifteen granted US/EP patent families. Marinissen is recipient of the Most Significant Paper Awards at ITC 2008 and ITC 2010, Best Paper Awards at the Chrysler-Delco-Ford Automotive Electronics Reliability Workshop 1995 and the IEEE International Board Test Workshop 2002, the Most Inspirational Presentation Award at the IEEE Semiconductor Wafer Test Workshop 2013, the HiPEAC Tech Transfer Award 2015, the SEMI Best ATE Paper Award 2016, and finalist for the National Instruments’ Engineering Impact Award 2017.
Marinissen served as Editor-in-Chief of IEEE Std 1500 and as Founder and Chair (currently Vice-Chair) of the IEEE Std P1838 Working Group on 3D test access. He is founder of the workshops ‘Diagnostic Services in Network-on-Chips’ (DSNOC), DATE’s Friday 3D Integration, and the IEEE ‘International Workshop on Testing Three-Dimensional Integrated Circuits’ (3D-TEST). He has been Program Chair of DDECS 2002, ETS 2006, 3D-TEST 2009-15, and DATE 2013, and General Chair of ETW 2003, DSNOC 2007-08, 3DIW 2009-10, and serves on numerous conference committees, including ATS, DATE, ETS, ITC, ITC-Asia and VTS. He serves on the editorial boards of IEEE ‘Design & Test’, IET ‘Computers and Digital Techniques’, and Springer’s ‘Journal of Electronic Testing: Theory and Applications’. He is a Fellow of IEEE and Golden Core Member of Computer Society.
Jörg Kiesewetter is Director of Engineering at Cascade Microtech GmbH, a FormFactor company, in Thiendorf, Germany. Jörg has a background in mechanical engineering. He started to work in the semiconductor equipment industry joining the Karl Süss Dresden GmbH in 1990. With his background in mechanical engineering he worked in different projects and roles like development of positioners, mask aligners, anodic bonders, and probe stations. He worked as a project leader in the field of development of a fully automatic PCB mask-aligner from 1995 to 2000. Since 2001 he is managing the engineering group of the Dresden branch of the Cascade Microtech GmbH. In this role his main focus is the development of fully automatic, semi-automatic, and manual probe stations for engineering and process monitoring applications. His ideas are involved in more than 10 patent families and he contributed to publications in particular in the field of 3D TSV and fine-pitch micro-bump testing, a field he is working in for 10 years.
Ken Smith is Principal Engineer at FormFactor, in Beaverton, Oregon. Ken’s professional focus is on high-performance test and measurement issues, primarily in the interconnect and test environment domains. Since joining Cascade Microtech in the early ’90s he has generated more than 50 papers and 40 patents. Key contributions include the MicroChamber, allowing femtoamp-level on-wafer measurements, and MicroScrub for the Pyramid Probe business unit he established. At Tektronix he designed products and processes for multi-GHz hybrids for oscilloscopes and ATE pin drivers, managed the hybrids circuits R&D and production operations, and built the first financially successful membrane probes for high-speed digitizer IC test. His current focus is on new test solutions for the extremely challenging designs allowed by 3D TSV and fine-pitch micro-bumps.